The present invention relates to a semiconductor device of a manufacturing technique of the same, and in particular to a semiconductor device having a power transistor with a trench gate structure and a manufacturing technique of the same.
The power MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) with a trench gate structure is a vertical power transistor constructed as follows: a gate electrode is formed in a trench dug in the direction orthogonal to the main surface of a semiconductor substrate with a gate insulating layer in-between; a source region is formed in the surface part of the main surface of the semiconductor substrate; a drain region is formed on the under side of the semiconductor substrate opposite to the main surface; and a channel is formed in the portion of the semiconductor substrate that is positioned between the source region and the drain region and to which the side face of the gate electrode in the trench is opposed.
An example of such a power MOS-FET with a trench gate structure is disclosed in Japanese Unexamined Patent Publication No. 2000-196075 (Patent Document 1). FIG. 19 in Patent Document 1 illustrates a construction in which the upper part of a gate electrode buried in a trench formed in a semiconductor substrate is protruded to a level higher than the main surface of the semiconductor substrate. FIG. 26 in Patent Document 1 illustrates a construction in which the following is implemented by taking the following measures: a first opening is formed in a semiconductor substrate. The first opening penetrates a third semiconductor layer 2c for source region in the superficial layer of the main surface of the semiconductor substrate and extends to a second semiconductor layer 2b for channel formation under the third semiconductor layer 2c. Part of the interlayer insulating film 7 on the periphery of the upper part of the first opening is selectively etched and removed to form a second opening in the interlayer insulating film 7. This second opening is so formed that an end of the interlayer insulating film 7 recedes away from the first opening and the third semiconductor layer 2c for source region in the superficial layer of the main surface of the semiconductor substrate is exposed. The area of contact between a source electrode 10 buried in the first and second openings and the third semiconductor layer 2c for source region formation in the superficial layer of the main surface of the semiconductor substrate is thereby increased. At the same time, the resistance of connection between the source electrode 10 and the third semiconductor layer 2c is reduced.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-196075 (FIG. 26 and so on)